There’s currently a significant buzz within the semiconductor industry around chiplets, bare silicon dies intended to be combined with others into a single packaged device. Companies are beginning to plan for chiplet-based designs, also known as multi-die systems. Yet, there is still uncertainty about what designing chiplet architecture entails, which technologies are ready for use, and what innovations are on the horizon.
Understanding the technology and supporting ecosystem is necessary before chiplets begin to see widespread adoption. As technology continues to emerge, chiplets are a promising solution for many applications, including high-performance computing, AI acceleration, mobile devices, and automotive systems.
Figure 1 Understanding the technology is necessary before chiplets begin to see widespread adoption. Source: Arteris
The rise of chiplets
Until recently, integrated circuits (ICs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), and system-on-chip (SoC) devices were monolithic. These devices are built on a single piece of silicon, which is then enclosed in its dedicated package. Depending on its usage, the term chip can refer to either the bare die itself or the final packaged component.
Designing monolithic devices is becoming increasingly cost-prohibitive and harder to scale. The solution is to break the design into several smaller chips, known as chiplets, which are mounted onto a shared base called a substrate. All of this is then enclosed within a single package. This final assembly is a multi-die system.
Building on this foundation, the following use cases illustrate how chiplet architectures are being implemented. Split I/O and logic is a chiplet use case in which the core digital logic is implemented on a leading-edge process node. Meanwhile, I/O functions such as transceivers and memory interfaces are offloaded to chiplets built on older, more cost-effective nodes. This approach, used by some high-end SoC and FPGA manufacturers, helps optimize performance and cost by leveraging the best technology for each function.
A reticle limit partitioning use case implements a design that exceeds the current reticle limit of approximately 850 mm2 and partitions it into multiple dies. For example, Nvidia’s Blackwell B200 graphics processing unit (GPU) utilizes a dual-chiplet design, where each die is approximately 800 mm² in size. A 10 terabytes-per-second link enables them to function as a single GPU.
Homogeneous multi-die architecture integrates multiple identical or functionally similar dies, such as CPUs, GPUs, or NPUs, on a single package or via an ‘interposer’, a connecting layer similar to a PCB but of much higher density and typically made of silicon using lithographic techniques. Each die performs the same or similar tasks and is often fabricated using the same process technology.
This approach enables designers to scale performance and throughput beyond monolithic die designs’ physical and economic limits, mainly as reticle limits of approximately 850 mm² constrain single-die sizes or decreasing yield with increasing die size makes the solution cost-prohibitive.
Functional disaggregation is the approach most people think of when they hear the word chiplets. This architecture disaggregates a design into multiple heterogeneous dies, where each die is realized at the best node in terms of cost, power, and performance for its specific function.
For example, a radio frequency (RF) die might be implemented using a 28 nm process, analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) could be realized in a 16 nm process, and the core digital logic might be fabricated using a 3 nm process. Large SRAMs may be implemented in 7 nm or 5 nm, as RAM has not scaled significantly in finer geometries.
The good news
There are multiple reasons why companies are planning to transition or have transitioned to chiplet-based architectures. These include the following:
- Chiplets can build larger designs than are possible on a single die.
- Higher yields from smaller dies reduce overall manufacturing costs.
- Chiplets can mix and match best-in-class processing elements, such as CPUs, GPUs, NPUs, and other hardware accelerators, along with in-package memories and external interface and memory controllers.
- Multi-die systems may feature arrays of homogeneous processing elements to provide scalability, or collections of heterogeneous elements to implement each function using the most advantageous process.
- Modular chiplet-based architectures facilitate platform-based design coupled with design reuse.
Figure 2 There are multiple drivers pushing semiconductor companies toward chiplet architectures. Source: Arteris
The ecosystem still needs to evolve
While the benefits are clear, several challenges must be addressed before chiplet-based architectures can achieve widespread adoption. While standards like PCIe are established, die-to-die (D2D) communication standards like UCIe and CXL continue to emerge, and ecosystem adoption remains uneven. Meanwhile, integrating different chiplets under a common set of standards is still a developing process, complicating efforts to build interoperable systems.
Effective D2D communication must also deliver low latency and high bandwidth across varied physical interfaces. Register maps and address spaces, once confined to a single die, now need to extend across all chiplets forming the design. Coherency protocols such as AMBA CHI must also span multiple dies, making system-level integration and verification a significant hurdle.
To understand the long-term vision for chiplet-based systems, it helps first to consider how today’s board-level designs are typically implemented. This usually involves the design team selecting off-the-shelf components from distributors like Avnet, Arrow, DigiKey, Mouser, and others. These components all support well-defined industry-standard interfaces, including I2C, SPI, and MIPI, allowing them to be easily connected and integrated.
In today’s SoC design approach, a monolithic IC is typically developed by licensing soft intellectual property (IP) functional blocks from multiple trusted third-party vendors. The team will also create one or more proprietary IPs to distinguish and differentiate their device from competitive offerings. All these soft IPs are subsequently integrated, verified, and implemented onto the semiconductor die.
The long-term goal for chiplet-based designs is an entire chiplet ecosystem. In this case, the design team would select a collection of off-the-shelf chiplets created by trusted third-party vendors and acquired via chiplet distributors rather as board-level designers do today. The chiplets will have been pre-verified with ‘golden’ verification IP that’s trusted industry-wide, enabling seamless integration of pre-designed chiplets without the requirement for them to be verified together prior to tape-out.
The team may also develop one or more proprietary chiplets of their own, utilizing the same verification IP. Unfortunately, this chiplet-based ecosystem and industry-standard specification levels are not expected to become reality for several years. Even with standards such as UCIe, there are many options and variants within the specification, meaning there is no guarantee of interoperability between two different UCIe implementations, even before considering higher-level protocols.
The current state-of-play
Although the chiplet ecosystem is evolving, some companies are already creating multi-die systems. In some cases, this involves large enterprises such as AMD, Intel, and Nvidia, who control all aspects of the development process. Smaller companies may collaborate with two or three others to form their own mini ecosystem. These companies typically leverage the current state-of-play of D2D interconnect standards like UCIe but often implement their own protocols on top and verify all chiplets together prior to tape-out.
Many electronic design automation (EDA) and IP vendors are collaborating to develop standards, tool flows, and crucially VIP. These include companies like Arteris, Cadence, Synopsys, and Arm, as well as RISC-V leaders such as SiFive and Tenstorrent.
Everyone is jumping on the chiplet bandwagon these days. Many are making extravagant claims about the wonders to come, but most are over-promising and under-delivering. While a truly functional chiplet-based ecosystem may still be five to 10 years away, both large and small companies are already creating chiplet-based designs.
Ashley Stevens, director of product management and marketing at Arteris, is responsible for coherent NoCs and die-to-die interconnects. He has over 35 years of industry experience and previously held roles at Arm, SiFive, and Acorn Computers.
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