Intel has made significant strides in implementing High-NA EUV lithography by installing two High-NA litho machines, developing custom reticles as well as all-new optical proximity correction, and processing 30,000 wafers. However, major hurdles remain: the $380 million – $400 million tool cost and potential necessity to overhaul photomask supply chain limits economic viability of the technology. Furthermore, a single High-NA EUV exposure costs 2.5 times more than a single Low-NA EUV exposure, which raises further questions about economic feasibility over the next few years, reports SemiAnalysis.
Puzzling economics
ASML’s Twinscan EXE:5000 weighs 150 tons and is priced around $380 million – $400 million, roughly double that of its Low-NA Twinscan NXE predecessors. At the SPIE conference earlier this year IBM presented simulation data comparing different approaches to patterning. It showed that replacing three or four Low-NA masks with one High-NA exposure could yield cost savings. For example, IBM estimated a four-mask self-aligned double patterning flow is 1.7 to 2.1 times more expensive than a single High-NA exposure. But when only two Low-NA passes are replaced, High-NA becomes more expensive by 2.5 times, which means that High-NA is only cost-efficient when it can eliminate three or more exposures.
This does not mean that the industry will not need High-NA tools. It means that the industry will have tangible benefits of using High-NA EUV lithography when it needs triple or quadruple patterning with Low-NA EUV scanners, which will depend on process technologies that the industry adopts and aggressiveness of process scaling going forward.
According to Intel, this may happen sooner rather than later. The company showed imaging results, made economic comparisons, and discussed patterning alternatives, and ecosystem readiness, painting a detailed picture of where High-NA EUV stands in 2025 at the SPIE Advanced Lithography conference earlier this year.
The imaging results included key device layers such as metal and contact levels. In the case of metal layers, Intel used one High-NA exposure to replace a previous scheme requiring three separate Low-NA exposures and around 30 total process steps. This simplification could reduce cost and defectivity for complex interconnect structures. In contact holes, yield from early High-NA tests matched that of established multi-patterning flows, despite the initial masks being early-stage test versions. These outcomes suggest High-NA EUV lithography is technically viable for some of the most challenging layers at upcoming nodes.
Intel itself is expected to selectively implement High-NA EUV lithography for a few layers within its Intel 14A (1.4nm-class) process technology, though ecosystem readiness could impact the company’s plans. For Intel, the good news is that it is at the helm of that ecosystem development and will therefore have a lead over rivals.
Parallel development
By acquiring and installing two ASML Twinscan EXE:5000 lithography tools ahead of competitors, Intel is ahead of the industry in gathering process data and proving viability for high-volume manufacturing. Intel did everything it could to get its High-NA EUV scanners as early as possible. It received the first Twinscan EXE:5000 machine over a year ago and skipped ASML’s typical factory tool qualification, which includes assembly of the tool at an ASML facility — opting instead for assembly and startup at its own D1D fab near Hillsboro, Oregon. This early decision gave Intel a head start in validating the system and building process readiness. To support its development efforts, Intel exposed over 30,000 wafers across both High-NA tools, making it the most experienced user of this new platform.
But getting a new scanner and assembling it are only some of the challenges associated with making it work properly. In addition, Intel needed to develop process technology itself, photomasks, resists, and optical proximity correction (OPC) software enhancement techniques. Normally, since all these things are co-dependent, they are developed serially. However, Intel adopted a parallel development strategy to meet the tight timeline for its 14A (1.4nm-class) node, which is expected to be production ready in 2026. The company shared details how it managed to do so at this year’s SPIE Advanced Lithography conference.
Intel began to develop OPC well before it got its High-NA EUV tool running. The company used simulations and exposures on conventional EUV tools to extrapolate and fine-tune models intended for High-NA EUV. This strategy bypassed the usual delay in mask preparation and enabled immediate pilot line operation once the High-NA scanners were up. Results exceeded expectations: source power reached 110% of target (a first for an ASML scanner at launch) and overlay alignment measured at 0.6nm, which is comparable (yet, not as precise) to mature Low-NA systems.
By now, Intel has made significant strides in developing production ready photomasks, resists, OCP, and other elements of High-NA EUV production flow. However, it looks like the obstacles associated with adoption of High-NA EUV tools by the industry are not only engineering challenges, but also economic hurdles associated both with infrastructure development and usage scenarios.
Not yet ready for prime time
One of the challenges with High-NA EUV lithography is the two times smaller exposure field compared to Low-NA EUV lithography due to higher numerical aperture of projection optics: 26 mm × 16.5 mm vs. 26 mm × 33 mm.
This is a major challenge for large chips like GPUs and CPUs, which often exceed the 13×26 mm limit of a single High-NA exposure. Therefore, to pattern these dies, two or more overlapping exposures (stitched fields) must be used (an alternative is to use a multi-chiplet designs). This introduces alignment complexity, risks of overlay errors, and yield loss in the stitched regions. Also, with fewer chips fit per exposure field, more passes per wafer are required, which reduces the wafer-per-hour rate and increases cost per wafer.
ASML proposes to use accelerated stages (i.e., accelerate how the wafer moves under the photomask) to compensate for higher number of exposures. However, Intel has long proposed to use a larger 6×12-inch photomask instead of industry-standard 6×6-inch photomask. A larger photomask solves the half-field problem by doubling the reticle area, allowing it to hold two adjacent half-field images side by side. When used with appropriately configured High-NA optics, this enables the system to expose a full 26 mm × 33 mm field in one scan pass, restoring the field size to that of Low-NA tools. This obviously eliminates the need for stitching and all the challenges associated with it.
However, the shift to larger photomasks would require a complete overhaul of the mask supply chain, from blank preparation and e-beam writing to handling and fab integration. ASML acknowledged that internal studies on larger masks are in progress but has not committed to bringing the capability to market. The change would disrupt the company’s platform unification strategy for Low-NA, High-NA, and eventually Hyper-NA tools and potentially reduce sales of higher-end tools.
In photoresist development, metal-oxide resists are gaining ground as the preferred option for High-NA, according to the Intel’s presentation at SPIE. These materials provide better performance in terms of resolution, line-edge roughness, and dose sensitivity, especially important given the thinner films required by the thin depth-of-focus associated with High-NA optics. Traditional chemically amplified resists struggle with etch resistance at the thicknesses now needed, while metal-oxide formulations retain sufficient durability during pattern transfer. Most SPIE 2025 data shared for High-NA tools used metal-oxide resists rather than legacy organics, according to SemiAnalysis.
The method of applying and developing photoresist is another point of industry concern. Tokyo Electron currently dominates the standard wet process with spin-on coating and wet development in its track tools. Lam Research is attempting to gain share by promoting a dry deposition and dry development approach, done in its proprietary tools.
Conclusion
While Intel plans to adopt High-NA EUV for its 14A node, the company itself has stated that 14A is possible using only Low-NA EUV lithography (albeit, with multipatterning). That said, broad deployment may be deferred until the 1.0nm-class generation, when further cost reduction, process maturity, and infrastructure upgrades are more likely to align. For now, Intel’s early investments grant it an advantage in know-how, giving it a strategic edge as the technology matures.
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