Implementing a simple digital-to-analog converter (DAC) by cascading a single pulse width modulator (PWM) and an analog low-pass filter is nothing new. Nor is applying to a filter the sum of the outputs of a most significant 2N-count PWM and a least significant 2N-count one to get a composite 22N-bit DAC [1][2]. But designing one with simple, adjustment-free topologies and reasonably accurate, repeatable performance characteristics is not trivial. A proposed example is seen in Figure 1. Let’s examine the circuit from the output to the input.
Figure 1 The PWM—driven 16-bit DAC. Capacitors C1, C2, and C3 are NPO/COG ceramic.
Wow the engineering world with your unique design: Design Ideas Submission Guide
Op amp
The OPA383 is a “rail-to-rail” input and output op amp. Typical of such parts, the output doesn’t quite swing to the rails. A close look at the spec reveals that the V+ and V- supplies should be at least ±155 mV beyond the range of output signals, and their difference should be less than 5.5 V. Input offset voltage is ±5 µV maximum at 25°C, but unfortunately, we are not given limits over temperature. However, a graph of 5 measured units shows limited susceptibility to temperature. Let’s assume three times 5, or a 15 µV maximum over the temperature range.
The bias current is ±76 pA maximum from -40°C to +85°C. I’d like to keep the design’s various independent error contributions under ½ PWM count (in this case, under 2-17 of full-scale). Considering the under 100 kΩ resistance seen by the op amp input, full-scale DAC voltages over 2.0 V would encounter errors less than ½ count due to bias current and offset voltage.
The op amp’s DC gain is a minimum of 118 dB, and its gain-bandwidth (GBW) product is 2.5 MHz typical. In the absence of other information, I’ll assume and work with a minimum GBW of 1 MHz.
PWM filter
The filter consists of U2, Ra, Rb1, Rb2, R1, R2, R3, C1, C2, and C3. It’s important to keep a handle on the tolerances of these passive components to ensure repeatable results. The capacitances of common ceramic types such as Y5V and X7R are very sensitive to temperature and to DC voltage; they are not recommended for use in filters requiring any significant stability. Film and ceramic COG/NPO types are far less sensitive. NPO/COG capacitors and the resistors of the values and tolerances shown in the schematic are available for well under $0.10 in 1000-piece quantities.
The filter shown is a 3rd-order one (evident from the presence of three capacitors). Generally, 3rd-order filters offer a smaller (better) product of settling time and ripple attenuation factor than 2nd-order filters (two capacitors). Design aids for 3rd-order types are rare, so I’ve used one I developed and published in EDN almost 15 years ago [3]. This filter does not rely on the cancellation of large signals of opposing phases, so there is no need for adjustment pots to deal with the lack of zero-tolerance components that would otherwise be required to achieve maximal nulling.
It’s the job of the filter to suppress the AC “ripple” of PWM signals, which are at their worst when the output is 50% of full scale. Minimization of settling time is also of interest. To assess the effects of variations due to component tolerances, Figure 2 and Figure 3 show 100-run Monte Carlo trials of settling times for a zero to full-scale transition and for ripple attenuation.
Figure 2 100 Monte Carlo runs of a transition from 0 to full scale, 0 to 65535 counts. Settling to better than ½ count occurs in less than 2 milliseconds.
Figure 3 100 Monte Carlo runs of ripple, where full scale is 65535 counts. Ripple is less than ½ PWM count peak and 1 count peak-to-peak. PWM frequency is 78 kHz.
Summing network
There are two 8-bit PWMs. To create a 16-bit signal, the contribution of the most significant PWM signal is weighted by a factor very close to 256 times larger than that of the less significant PWM signal. A summing network of Ra and Rb1 + Rb2 accomplishes this. (Note that the remaining filter components have no DC effect on this network.)
Filter drivers (logic Inverters)
The logic inverters shown driving the summing network have finite output resistances, which effectively add to those of Ra and R1b. Unfortunately, logic inverters are not linear devices and are not characterized as such. The best way to determine maximum output resistance from their data sheets is to first identify the specified supply voltage nearest (but less than or equal) to the one intended for use, and then divide the maximum output voltage drop by the specified load current.
It’s best to do this for the high side, as its resistance is typically higher than that of the low side. For instance, if a 3.3-V supply is intended for a Texas Instruments SN74AC04, use the datasheet’s 2.46-V minimum for a 3-V supply drawing 12 mA to arrive at a maximum resistance of 45 Ω. Paralleling five gates will reduce that resistance to an unknown amount below 9 Ω. The amount is unknown because the individual inverters share common resistances on the wafer and in the wafer-to-package bonding wires. And so up to 9 Ω is added to Ra. The up to 45 Ω added to Rb has a comparably negligible effect.
But here we depart from the goal of limiting an error source to a maximum contribution of ½ count—the maximum differential non-linear error is now just under 1 count. Fortunately, even with this error, an increasing series of counts yields a monotonically rising sequence of output voltages. If the performance improvement is worth the cost, you could stay below a ½ count error by doing the following:
- Replacing the inverter with the low-resistance, dual-channel TS5A22362DRCR analog switch
- Replacing the R1a1% part with a 0.05% part
- Replacing the 30.1 kΩ R1b with a 28.7 kΩ 1% resistor in series with a 5% 510-Ω unit.
Driver power supply
Alas, once again, we must abandon the goal of keeping the errors introduced to less than ½ LSb. The TI REF35 IC’s ±0.05% at 25°C rating equates to 33 LSb’s! And even with the benefit of calibration and added hardware to adjust the inverter/analog switch’s supply voltage, the reference’s 12 ppm/°C temperature variations would leave us in the lurch. Once again, we have to eat some error.
In the spirit of continuing to do our best with the cards dealt, the reference’s DC resistance (60 ppm max of 3.3 V (for instance) / 1 mA) is about only 0.2 Ω. This is negligible when met with the DC resistance seen through the summing network of Ra and Rb. Transients from the inverters are a concern, however.
Adequate decoupling of those devices is a must. Additionally, the AC impedance due to the combination of R1, Ra Rb, and C1 of approximately Zsum = 16.5 kΩ appears at the inverter outputs and so also across their supply terminals. Fortunately, these are at frequencies no lower than the PWM frequency (see next section for this value). The capacitors shown keep the impedance at this frequency well below 0.1% of the almost completely resistive Zsum. For practical considerations, the magnitude of this combination is indistinguishable from that of Zsum.
PWM signal source
The PWM signal source is probably a microprocessor. These days, most of them can be clocked at 20 MHz or greater, meaning that they could all source 8-bit PWMs of at least 20 MHz / 256 = 78 kHz. It’s this frequency or higher that the filter was designed for. So why not use microprocessor GPIO PWM outputs as drivers?
First, there’s the usually fairly high GPIO output resistance. Additionally, if you’ve ever looked closely at the voltage of a microprocessor digital output, you might have seen that it’s a few millivolts or even tens of millivolts from ground and the device’s supply. This is because the processor is performing functions in addition to generating a PWM, which draw significant current, producing voltage drops through portions of the IC wafer and its package bonding wires. The SN74AC74 has no such other functions, and any such voltage drops are part of the voltage drop specs discussed earlier.
Modifications
Want lower ripple amplitude? Increase the PWMs’ frequency. Want faster settling time? The resistance looking into Ra and Rb is Rab = 4009 Ω. Reduce R3, R2, and R1—Rab by some factor and/or C1, C2, and C3 by the same or different factor. Increase the PWMs’ frequency by at least the product of the factors. Increase it further to achieve both improvements.
To sum it up
A simple design has been introduced for a PWM-driven 16-bit DAC. Peak ripple is less than ½ LSb and the circuit settles to this level in less than 2 ms. Monte Carlo analyses show that these parameters are met even considering passive component and op amp GBW tolerances. In 1k quantities, the reference is about $1, the op amp is under $0.75, and the filter passives are each under $0.10.
Error sources in various parts of the circuit have been identified and, where possible, limited to no more than ½ LSb. To address other larger errors, suggestions of additional hardware and calibration have been made, but the temperature sensitivity of the voltage reference is a limiting factor.
Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.
Related Content/References
- Double up on and ease the filtering requirements for PWMs
- Inherently DC accurate 16-bit PWM TBH DAC
- Design second- and third-order Sallen-Key filters with one op amp
The post A nice, simple, and reasonably accurate PWM-driven 16-bit DAC appeared first on EDN.
