How AI is changing the game for high-performance SoC designs

The need for intelligent interconnect solutions has become critical as the scale, complexity, and customizability of today’s systems-on-chip (SoC) continue to increase. Traditional network-on-chip (NoC) technologies have played a vital role in addressing connectivity and data movement challenges, but the growing intricacy of designs necessitates a more advanced approach. Especially, when high-end SoC designs are surpassing the human ability to create NoCs without smart assistance.

The key drivers for this demand can be summarized as follows:

• Application-specific requirements: Many industries and applications, such as automotive, Internet of Things (IoT), consumer electronics, artificial intelligence (AI), and machine learning (ML), require highly specialized hardware tailored to unique workloads, such as real-time processing, low latency, or energy efficiency. Off-the-shelf chips often fall short of providing the precise blend of performance, power, and cost-efficiency these applications need.
• Cost and performance optimization: Custom SoCs allow companies to integrate multiple functions into a single chip, reducing system complexity, power consumption, and overall costs. With advanced process nodes, custom SoCs can achieve higher levels of performance tailored to the application, offering a competitive edge.
• Miniaturization and integration: Devices in areas like wearables, medical implants, and IoT sensors demand miniaturized solutions. Custom SoCs consolidate functionality onto a single chip, reducing size and weight.
• Data-centric and AI workloads: AI and ML require processing architectures optimized for parallel computation and real-time inferencing. Custom SoCs can incorporate specialized processing units, like neural network accelerators or high-bandwidth memory interfaces, to handle these demanding tasks.

The market now demands a next-level approach, one that leverages AI and ML to optimize performance, reduce development time, and ensure efficient data movement across the entire system. Today’s high-end SoC designs are necessitating smarter, automated solutions to address evolving industry needs.

The solution is the introduction of a new type of smart NoC interconnect IP that can leverage smart heuristics using ML and AI technology to dramatically speed up the creation and increase the quality of efficient, high-performance SoC designs.

Today’s NoC technologies

Each IP in an SoC has one or more interfaces, each with its own width and frequency. A major challenge is the variety of standard interfaces and protocols, such as AXI, AHB, and APB, used across the industry. Adding to this complexity, SoCs often integrate IPs from multiple vendors, each with different interface requirements.

NoC technology helps manage this complexity by assigning a network interface unit (NIU) to each IP interface. For initiator IPs, the NIU packetizes and serializes data for the NoC. For target IPs, it de-packetizes and de-serializes incoming data.

Packets contain source and destination addresses, and NoC switches direct them to their targets. These switches have multiple ports, allowing several packets to move through the network at once. Buffers and pipeline stages further support data flow.

Without automation, designers often add extra switches, buffers, or pipeline stages as a precaution. However, too many switches waste area and power, excessive buffering increases latency and power use, and undersized buffers can cause congestion. Overusing pipeline stages also adds delay and consumes more power and silicon.

Existing NoC interconnect solutions provide tools for manual optimization, such as selecting topology and fine-tuning settings. However, they still struggle to keep pace with the growing complexity of modern SoCs.

Figure 1 SoC design complexity which has surpassed manual human capabilities, calls for smart NoC automation. Source: Arteris

Smart NoC IP

The typical number of IPs in one of today’s high-end SoCs ranges from 50 to 500+, the typical number of transistors in each of these IPs ranges from 1 million to 1+ billion, and the typical number of transistors on an SoC ranges from 1 billion to 100+ billion. Furthermore, modern SoCs may comprise between 5 to 50+ subsystems, all requiring seamless internal and subsystem-to-subsystem communication and data movement.

The result of all this is that today’s high-end SoC designs are surpassing human ability to create their NoCs without smart assistance. The solution is the introduction of a new type of advanced NoC IP, such as FlexGen smart NoC IP from Arteris. The advanced IP can leverage smart heuristics using ML technology to dramatically speed up the creation and increase the quality of efficient, high-performance SoC designs. A high-level overview of the smart NoC IP flow is illustrated in Figure 2.

Figure 2 A high-level overview of the FlexGen shows how smart NoC IP flow works. Source: Arteris

Designers start by using an intuitive interface to capture the high-level specifications for the SoC (Figure 2a). These include the socket specifications, such as the widths and frequencies of each interface. They also cover connectivity requirements, defining which initiator IPs need to communicate with which target IPs and any available floorplan information.

The designers can also specify objectives at any point in the form of traffic classes and assign performance goals like bandwidths and latencies to different data pathways (Figure 2b).

FlexGen’s ML heuristics determine optimal NoC topologies, employing different topologies for different areas of the SoC. The IP automatically generates the smart NoC architecture, including switches, buffers, and pipeline stages. The tool minimizes wire lengths and reduces latencies while adhering to user-defined constraints and performance goals (Figure 2c). Eventually, the system IP can be used to export everything for use with physical synthesis (Figure 2d).

NoC with smart assistant

The rapid increase in SoC complexity has exceeded the capabilities of traditional NoC design methodologies, making it difficult for engineers to design these networks without smart assistance. This has driven the demand for more advanced solutions.

Take the case of FlexGen, a smart NoC IP from Arteris, which addresses these challenges by leveraging intelligent ML heuristics to automate and optimize the NoC generation process. The advanced IP delivers expert-level results 10x faster than traditional NoC flows. It reduces wire lengths by up to 30%, minimizes latencies typically by 10% or more, and improves PPA metrics.

Streamlining NoC development accelerates time to market and enhances engineering productivity.

Andy Nightingale, VP of product management and marketing at Arteris, has over 37 years of experience in the high-tech industry, including 23 years in various engineering and product management positions at Arm.

Related Content

• SoC Interconnect: Don’t DIY!
• What is the future for Network-on-Chip?
• SoC design: When is a network-on-chip (NoC) not enough
• Network-on-chip (NoC) interconnect topologies explained
• Why verification matters in network-on-chip (NoC) design

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