Dynamic random-access memory (DRAM) chips contain many other transistors besides the access transistor to enable full operation of the DRAM memory. These peripheral transistors must meet stringent requirements which preclude a ‘copy-paste’ of regular logic transistor process flows.
One critical requirement imposed by present DRAM chip architectures is the ability of the periphery to withstand thermal treatments at 550-600°C and above. While the first part of this article series focused on DRAM basics and peripheral circuits, this part will provide a detailed account of DRAM periphery, explaining different generations of thermally stable peripheral transistor technology ranging from planar high-k/metal-gate transistors to FinFETs.
DRAM periphery: From SiON-based gate stacks to high-k/metal gates
Until 2018, DRAM peripheral transistors were predominantly made in planar logic MOSFET technology with poly-Si/SiO2 or poly-Si/SiON gates. These technologies were less advanced than the transistors used for high-performance logic in order to maintain the DRAM cost-per-bit trendline.
However, an improved technology for the periphery became necessary to keep pace with the performance enhancement enabled by subsequent generations of DRAM memory. The most obvious candidate was moving to a planar transistor architecture with a high-k/metal-gate stack—a transition that occurred as early as 2007 in the high-volume manufacturing of logic technologies.
Since about 2007, imec, together with its partners, has actively explored a DRAM-compatible version of high-k/metal-gate transistors and proposed multiple material and integration options to the memory industry. Today, almost every device with a DRAM memory inside contains a planar peripheral transistor technology with high-k/metal gates, which imec has been pioneering for more than 15 years.
Below is a grasp of some of the proposed material, module, and integration options, all differing in fabrication complexity and performance levels.
High-k/metal-gate integration: Thermally stable gate-first and gate-last integration flows
One of the solutions demonstrated by imec for potential early introduction was based on a gate-first integration approach, in which the metal gate is deposited before the high-temperature source/drain junction activation anneal. Gate stacks for nMOS and pMOS can be optimized separately by using different work function metals and layer thicknesses for the high-k/metal-gate stack (for example, TiN/Mg/TiN for n; TiN for p).
One of the critical parameters is obtaining an effective work function that is low enough for nMOS and high enough for pMOS to ensure a good Ion/Ioff ratio. Researchers achieved this by doping the gate stacks (with different dopants for pMOS and nMOS), which enabled a shift in the threshold voltages.
The choice of the dopant materials and their integration also provided a knob for improving the thermal stability of the gate stack and enabling the different Vth required by the DRAM chip. The DRAM-specific requirement for low gate leakage was addressed, among others, by adopting thicker gate stacks compared to logic-oriented solutions.
Figure 1 Sketch of the critical fabrication steps is shown in a gate-first integration approach for planar high-k/metal-gate peripheral transistors. Source: PSS
Imec also successfully demonstrated a thermally improved version of a gate-last integration approach, also called replacement metal gate (RMG) flow. In a gate-last flow, a poly-Si capped dummy gate is deposited and remains in place until the junction activation anneal is applied. After that, the dummy poly is replaced by the target metal gate.
Optimized source/drain junctions
Source/drain junctions are critical to ensure the functionality of MOSFET transistors. They are formed by creating a dopant gradient in the source/drain areas. As conduction channel lengths continued to shrink, ultra-shallow junctions became indispensable to ensure good electrostatic control over the channel. However, for peripheral transistors, the thermal treatments during DRAM memory anneal trigger an unwanted diffusion of the dopants, requiring more complex process flows to maintain the dopant gradient.
This issue can be addressed by changing the junction implant scheme using, for example, pre-amorphization implants and junction co-implants. Imec demonstrated several sets of optimized junctions suited for various threshold voltage targets.
A thermally stable silicide process
A general challenge for all transistors is to keep the source/drain contact resistance as low as possible. Source/drain contacts are formed by bringing a metal in contact with the source/drain regions, creating a Schottky barrier at the interface.
To ensure low resistance, two techniques are typically applied: (1) heavy doping of the source/drain regions and (2) complete silicidation of the source/drain areas—the silicides being formed through the reaction of the contact metal with the doped Si.
However, Ni(Pt) silicide, traditionally used in logic devices, cannot withstand the DRAM-related anneal temperatures. Imec proposed a thermally stable NiPt-based silicide module with low contact resistance by implementing additional implants and annealing steps for silicide stabilization.
Thermally stable, FinFET-based peripheral platform
Applications like automotive, artificial intelligence (AI) and machine learning (ML) impose increasingly stringent requirements on DRAM memories, driving the need for faster, more reliable and power efficient peripheral transistors. One option is to retrace the path of ‘logic’ and move from planar high-k/metal-gate transistors to FinFETs.
The logic roadmap made this transition as early as 2011 after R&D clearly showed the superior performance of transistors with fin-shaped conduction channels: improved Ion/Ioff, better short channel control, higher drive current at reduced footprint (due to a higher effective width of the channel), and lower power consumption—while keeping cost under control. On top of that, the use of tall fins provides a way to reduce the threshold voltage mismatch, which can particularly benefit the DRAM sense amplifiers.
Just like for the planar versions, the DRAM-specific requirements preclude a copy-paste of FinFET process flows developed for regular logic. In response, imec developed a thermally stable FinFET-based peripheral technology platform with integrated modules optimized for DRAM. Multiple flavors with different performance-cost trade-offs have been proposed to the industry for their next-generation DRAM products.
Thermally stable gate-first and gate-last FinFET integration flows
In 2021, imec reported the first experimental demonstration of a thermally robust integration flow for FinFETs using an optimized gate-first approach for implementing the high-k/metal-gate stack. Compared to a traditional gate-first approach, the modified flow implements gate stacks with the same thickness and the same work function metal for both nMOS and pMOS. So-called Vth shifter materials are then diffused into the high-k dielectric to tune the effective work function of the nMOS and pMOS devices.
This modified gate-first approach reduces the gate asymmetry and enhances the thermal stability of the flow. By using this flow, the researchers demonstrated improved Ion/Ioff and short channel control over planar high-k/metal-gate counterparts. These metrics did not degrade after the DRAM-specific anneal. Flavors with taller fins (with up to 80-nm height) have also been developed, with improved threshold voltage mismatch and area gain.
Figure 2 Example of a fabricated high-k/metal-gate fin displays transmission electron microscope (TEM) cross sections for 40-nm, 65-nm, and ~80-nm tall fins. Source: imec
A drawback of the gate-first integration approach is the relatively high threshold voltage, which originates from the impact of the high-temperature anneal on the gate stack during junction activation. This issue can be solved using a gate-last (or RMG) integration approach, which, however, comes with additional process steps. At IEDM in 2022, imec showed a thermally stable version of a FinFET gate-last flow.
Figure 3 The above image shows a selection of relevant process step for the proposed gate-last process flow for thermally stable FinFETs. Source: 10.1109/IEDM45625.2022.10019422
An optimized and thermally stable gate-last FinFET flow with a Mo-based work function metal for pMOS
Typical for a gate-last flow is the use of different work function metals for nMOS and pMOS devices. At VLSI in 2024, imec demonstrated the performance benefits of using a novel Mo-based work function metal for pMOS instead of the conventional TiN-based approach. The new gate stack module was successfully integrated into a gate-last FinFET flow and proven to be thermally stable.
The DRAM-compatible flow with integrated Mo-based p-work function metal yielded sufficiently low Ioff current and low threshold voltage (0.12 V) for the pMOS devices. The FinFETs were also benchmarked against a thermally stable planar high-k/metal-gate reference, showing a three times higher Ion (at target Ioff) for the same Si footprint. These results make the thermally stable gate-last FinFET flow a valuable candidate for sub-10 nm DRAM peripheral logic.
Figure 4 On left and middle are TEM images across fins on a ring oscillator and on right is elemental mapping across gate (EDS) showing CMOS patterning and decent conformality of the Mo-based p-work function metal stacks. Source: VLSI 2024
Thermally stable Nb-based metal contacts with low contact resistance
In earlier work on planar high-k/metal-gate based peripheral transistors, imec researchers lowered the source/drain contact resistance by improving the dopant profile and adding pre-amorphization implants. At IEDM in 2024, imec introduced a different approach: replacing the conventional Ti contact metal with Nb for pMOS devices.
The thermal stability of the Nb-based contact module was demonstrated for the first time. In addition, superior performance was observed when integrated into the gate-last FinFET platform: record low contact resistance, reduced overall parasitic resistance, and improved Ion.
Figure 5 The above chart shows a comparison of the contact resistivities of Ti- and Nb-based contact modules (different thicknesses) for before and after DRAM anneal. Source: IEDM 2024
Ahead of DRAM mass production
Imec pioneered peripheral transistor technology 10 years ahead of the industry’s mass production introduction. In its most recent R&D work, imec demonstrated an industry-relevant, thermally stable FinFET-based platform to meet the requirements for sub-10 nm DRAM. Multiple flavors have been developed as possible solutions for next-generation DRAM products, providing different levels of fabrication complexity and transistor performance.
More disruptive concepts are envisioned in the longer term to continue the DRAM scaling path. One of these is building the periphery on a separate wafer and integrating it with the memory array using advanced wafer bonding techniques. Although this approach comes with additional process steps, a true benefit is the relaxed requirement for thermal stability, as the periphery is now manufactured separately from the memory array.
Imec recently initiated R&D work on peripheral transistors for this new DRAM architecture, guided by insights obtained from planar and FinFET-based technology.
Alessio Spessot, technical account director, has been involved in developing advanced CMOS, DRAM, NAND, emerging memory array, and periphery during his stints at Micron, Numonyx, and STMicro.
Naoto Horiguchi, director of CMOS device technology at imec, has worked in Fujitsu and the University of California Santa Barbara while being involved in advanced CMOS device R&D.
Related Content
- DRAM gets more exotic
- FCRAM 101: Understanding the Basics
- DRAM: the field for material and process innovation
- Winbond’s innovative DRAM design and the legacy of Qimonda
- DRAM technology for SOC designers and—maybe—their customers
googletag.cmd.push(function() { googletag.display(‘div-gpt-ad-native’); });
–>
The post A new platform for thermally stable DRAM peripheral transistors appeared first on EDN.
