Ensuring stable power management is crucial in modern electronics, and the power supply rejection ratio (PSRR) plays a key role in achieving this. This article serves as a practical guide to measuring PSRR for power management ICs (PMICs) and offering clear and comprehensive instructions.
PSRR reflects a circuit’s ability to reject fluctuations in its power supply voltage, directly impacting performance and reliability. By understanding and accurately measuring this parameter, engineers can design more robust systems that maintain consistent operation even under varying power conditions.
Figure 1 Here is the general methodology to measure PSRR. Source: Renesas
PSRR is a vital parameter that assesses an LDO’s capability to maintain a consistent output voltage amidst variations in the input power supply. Achieving high PSRR is crucial in scenarios in which the input power supply experiences fluctuations, thereby ensuring the dependability of the output voltage. Figure 1 below illustrates the general methodology for measuring PSRR.
The mathematical expression to calculate the PSRR value is:
PSRR = 20 log10 VIN/VOUT
Where VIN and VOUT are the AC ripple of the input and output voltage, respectively.
Equipment and setup
To ensure an accurate measurement of the PSRR, it’s essential to set up the test environment with precision. The following design outlines the use of the listed equipment to establish a robust and reliable test configuration.
First, connect the power supply—in our case it’s a Keithley 2460—to the input of the Picotest J2120A line injector. The power supply should be configured to generate a stable DC voltage while the AC ripple component is provided by a Bode 100 network analyzer output using the J2120A line injector to simulate power supply variations.
Note that J2120A line injector includes an internally biased N-channel MOSFET. This means that there is a voltage drop between the J2120A input and output. The voltage drop is non-linear, and its dependency is shown on Figure 2. This means that each time the load current is adjusted, the source power supply must also be adjusted to maintain a constant DC output voltage at the J2120A terminals.
Figure 2 J2120A’s resistance and voltage drop is shown versus output current. Source: Renesas
For example, to get 1.2 V at the input of the LDO regulator, and depending on the current load, it might be required to set the voltage on the input of the line injector from 2.5 V to 3.5 V. The MOSFET operates as open loop so not to become unstable when connected to the external regulator.
Next, a digital multimeter is used to monitor both the input and output voltages of the PMIC. Ensure that proper grounding is used, and minimal interference is present in the connections to maintain measurement integrity.
Finally, a Bode 100 from Omicron Lab is used to record and analyze the measurements. This data can be used to compute the PSRR values and evaluate the PMIC’s ability to maintain a stable output despite variations in the input supply.
By carefully following this setup, one can ensure accurate and reliable PSRR measurements, contributing to the development of high-performance and dependable electronic systems.
Table 1: Here is an outline of the instruments used in PSRR measurements. Source: Renesas
Table 2 See the test conditions for LDOs. Source: Renesas
Settings for PSRR bench measurements setup
Figure 3 Block diagram shows the key building blocks of PSRR bench measurement. Source: Renesas
The PSRR measurement is performed with the Bode 100. The Gain/Phase measurement type should be chosen in the Bode Analyzer Suite software as shown on Figure 4.
Figure 4 Start menu is shown in the Bode Analyzer Suite software. Source: Renesas
Set the Trace 1 format to Magnitude (dB).
Figure 5 This is how to set Trace 1. Source: Renesas
To get the target PSRR measurement, choose the following settings in the “Hardware Setup”:
- Frequency: Change the Start frequency to “10 Hz” and Stop frequency to “10 MHz”.
- Source mode: Choose between Auto off or Always on. In Auto off mode, the source will be automatically turned off whenever it’s not used (when a measurement is stopped). In Always on mode, the signal source stays on after the measurement has finished. This means that the last frequency point in a sweep measurement defines the signal source frequency and level.
- Source level: Set the constant source level to “-16 dB” or higher for the output level. The unit can be changed in the options. By default, the Bode 100 uses dBm as the output level unit. 1 dBm equals 1 mW at 50 Ω load. “Vpp” can be chosen to display the output voltage in peak-to-peak voltage. Note that the internal source voltage is two times higher than the displayed value and valid when a 50 Ω load is connected to the output.
- Attenuator: Set the input attenuators 20 dB for Receiver 1 (Channel 1) and 0 dB for Receiver 2 (Channel 2).
- Receiver bandwidth: Select the receiver bandwidth used for the measurement. Higher receiver bandwidth increases the measurement speed. Reduce the receiver bandwidth to reduce noise and to catch narrow-band resonances.
Figure 6 The above diagram shows hardware setup in Gain/Phase Measurement mode and measurement configuration. Source: Renesas
Before starting the measurement, the Bode 100 needs to be calibrated. This will ensure the accuracy of the measurements. Press the “Full Range Calibration” button as shown in Figure 7. To achieve maximum accuracy, do not change the attenuators after external calibration is performed.
Figure 7 Press the “Full Range Calibration” button to ensure measurement accuracy. Source: Renesas
Figure 8 Here is how Full Range Calibration Window looks like. Source: Renesas
Connect OUTPUT, CH1, and CH2 as shown below and perform the calibration by pressing the Start button.
Figure 9 In calibration setup, Connect OUTPUT, CH1 and CH2, and press the Start button. Source: Renesas
Figure 10 This is how performed Calibration Window looks like. Source: Renesas
For all LDOs:
- The input capacitor will filter out some of the signals injected into the LDO, so it’s best to remove the input capacitors for the tested LDO or keep one as small as possible.
- Configure the network analyzer; use the power supply to power the line injector and connect the output of the network analyzer to the open sound control (OSC) input of the line injector.
- Power up the device under test (DUT) and configure the tested LDO’s output voltage. To prevent damage to the PMIC, the LDO’s input voltage should be less than or equal to the max input voltage. It’s highly recommended to power up the LDO without a resistive load, then apply the load and adjust the input voltage.
- Configure the LDO VOUT as specified in Table 2.
- Enable the LDO under test and use a voltmeter to check the output voltage.
- To ensure that the start-up current limit does not prevent the LDO from starting correctly, connect the resistive load to the LDO once the VOUT voltage has reached its max level.
- Adjust the voltage at the J2120A OUT terminals to their target VIN.
- Connect the first channel (CH1) of the network analyzer to the input of the LDO under test using a short coaxial cable.
- Connect the second channel (CH2) of the network analyzer to the output of the LDO under test using a short coaxial cable.
- Monitor the output voltage of the line injector on an oscilloscope. Perform a frequency sweep and check that the minimum input voltage and an appropriate peak to peak level for test are achieved. Make sure that the AC component is 200 mVpp or lower.
Figure 11 This simplified example shows headroom impact on the ripple magnitude. Source: Renesas
Note that headroom for the PSRR is not the same as the dropout voltage parameter (Vdo) specified in the datasheets (see Figure 11). Headroom in the context of PSRR refers to the additional voltage margin above the output voltage that an LDO requires to effectively reject variations in the input voltage.
Essentially, it ensures that the LDO can maintain a stable output despite fluctuations in the input power supply. Dropout voltage (Vdo), on the other hand, is a specific parameter defined in the datasheets of LDOs.
It’s the minimum difference between the input voltage (VIN) and the output voltage (VOUT) at which the LDO can still regulate the output voltage correctly under static DC conditions. When the input voltage drops below this minimum threshold, the LDO can no longer maintain the specified output voltage, leading to potential performance issues.
Figure 12 Example highlights applied ripple and its magnitude with DC offset for LDO’s input. Source: Renesas
- Set up the network analyzer by using cursors to measure the PSRR at each required frequency (1 kHz, 100 kHz and 1 MHz). Add more cursors if needed to measure peaks as shown in Figure 13.
Figure 13 This is how design engineers can work with cursors. Source: Renesas
- Capture images for each measured condition.
Figure 14 Example shows captured PSRR graph for the SLG51003 LDO. Source: Renesas
Figure 15 Bench measurement setup is shown for the SLG51003 PSRR.
Clear and precise PSRR measurement
This methodology provides a clear and precise approach for measuring the PSRR for the SLG5100X family of PMICs using the Omicron Lab Bode 100 and Picotest J2120A. Accurate PSRR measurements in the 10 Hz to 10 MHz frequency range are crucial for validating LDO performance and ensuring robust power management.
The accompanying figures serve as a valuable reference for setup and interpretation, while strict adherence to these guidelines enhances measurement reliability. By following this framework, engineers can achieve high-quality PSRR assessments, ultimately contributing to more efficient and reliable power management solutions.
Oleh Yakymchuk is applications engineer at Renesas Electronics’ office in Lviv, Ukraine.
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